1. Scope of the Invention
The invention relates generally to the data processing field and more particularly to the apparatus for aligning operands being transferred between a central processing unit and memory.
2. Prior Art
Present day data processing systems include a number of central processor subsystems, each incorporated in a semi-conductor chip. The systems will include one or more memory subsystems. Typically, the subsystems are coupled in common to a system bus. However, a cache memory may be coupled between the system bus and one or more of the central processor subsystems by external logic which performs an alignment operation on operands.
Operands are stored in memory as 8 bit bytes, 16 bit words, or 32 bit double words. Operands are stored in word locations. A double word is stored in memory locations having successive addresses starting with an even numbered address or an odd numbered address. Operands are transferred between the central processing unit and memory over a 32 bit bus. The contents of even numbered address locations are transferred over the 16 high order bit bus positions and the contents of odd numbered address locations are transferred over the 16 low order bit bus positions. This defines a word boundary as starting at an even numbered address location.
An operand alignment problem arises when a word operand starts at an even numbered address location. In that case the word operand must be switched over to the 16 low order bit bus positions. The alignment problem is even more complicated when a double word starts at an odd numbered address location. This requires that the high order word stored in the odd numbered address location be switched to the 16 high order bit bus positions and the low order word in the even numbered address location be switched to the 16 low order bit bus positions.
Previous designs included multiplexers selecting operands read from a cache memory and stored in a register. The operand stored in the register was then used in the execution of the instruction. However this presented a number of timing problems which reduced the system throughput.
Typical solutions to the operand alignment problem area described in U.S. Pat. No. 4,276,596 entitled "Short Operand Alignment and Merge Operation" and U.S. Pat. No. 4,240,144 entitled "Long Operand Alignment and Merge Operation".